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gal ? 22lv10 device datasheet june 2010 all devices discontinued! product change notifications (pcns) have been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modi fied and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn gal22lv10c-7lj gal22lv10c-7ljn pcn#06-07 gal22lv10c-10lj gal22lv10c-10ljn gal22lv10c-15lj gal22lv10c gal22lv10c-15ljn discontinued pcn#09-10 gal22lv10d-4lj gal22lv10d-4ljn gal22lv10d-5lj gal22lv10d gal22lv10d-5ljn discontinued pcn#09-10 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
1 gal22lv10 low voltage e 2 cmos pld generic array logic? 228 nc i/clk i i i i i i i i nc nc nc gnd i i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i/o/q i/o/q 42 6 25 19 18 21 23 16 14 12 11 9 7 5 features ? high performance e 2 cmos ? technology ? 4 ns maximum propagation delay ? fmax = 250 mhz ? 3 ns maximum from clock input to data output ? ultramos ? advanced cmos technology ? 3.3v low voltage 22v10 architecture ? jedec-compatible 3.3v interface standard ? 5v compatible inputs ? i/o interfaces with standard 5v ttl devices (gal22lv10c) ? active pull-ups on all pins (gal22lv10d) ?e 2 cell technology ? reconfigurable logic ? reprogrammable cells ? 100% tested/100% yields ? high speed electrical erasure (<100ms) ? 20 year data retention ? ten output logic macrocells ? maximum flexibility for complex logic designs ? programmable output polarity ? preload and power-on reset of all registers ? 100% functional testability ? applications include: ? glue logic for 3.3v systems ? dma control ? state machine control ? high speed graphics processing ? standard logic speed upgrade ? electronic signature for identification ? lead-free package options programmable and-array (132x44) i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i/clk i i i i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc gal22lv10 top view plcc copyright ? 2008 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2008 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com description the gal22lv10d, at 4 ns maximum propagation delay time, pro- vides the highest speed performance available in the pld market. the gal22lv10c can interface with both 3.3v and 5v signal levels. the gal22lv10 is manufactured using lattice semiconductor's advanced 3.3v e 2 cmos process, which combines cmos with electrically erasable (e 2 ) floating gate technology. high speed erase times ( < 100ms) allow the devices to be reprogrammed quickly and efficiently. the generic architecture provides maximum design flexibility by allowing the output logic macrocell (olmc) to be configured by the user. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lattice semiconductor delivers 100% field programmability and function- ality of all gal products. in addition, 100 erase/write cycles and data retention in excess of 20 years are specified. 22lv10_07 new 5v tolerant inputs on 22lv10d functional block diagram pin configuration all devices discontinued
specifications gal22lv10 2 gal22lv10 ordering information part number description blank = commercial grade package power l = low power speed (ns) xxxxxxxx xx x x x device name _ j = plcc jn = lead-free plcc gal22lv10d gal22lv10c conventional packaging commercial grade specifications lead-free packaging commercial grade specifications 1. discontinued per pcn #06-07. contact rochester electronics for available inventory. )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 433 0 3 1j l4-d01vl22la gc clpdael-82 55 . 35 . 30 3 1j l5-d01vl22la gc clpdael-82 5. 75 . 655 7j l7-c01vl22lag 1 cclpdael-82 0 15 . 75 . 65 7j l01-c01vl22la gc clpdael-82 5 10 10 15 7j l51-c01vl22la gc clpdael-82 )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 433 0 3 1n jl4-d01vl22la gc clpdael-82eerf-dael 55 . 35 . 30 3 1n jl5-d01vl22la gc clpdael-82eerf-dael 5. 75 . 655 7n jl7 - c01vl22lag 1 cclpdael-82eerf-dael 0 15 . 75 . 65 7n jl01-c01vl22la gc clpdael-82eerf-dael 5 10 10 15 7n jl51-c01vl22la gc clpdael-82eerf-dael all devices discontinued
specifications gal22lv10 3 gal22lv10 output logic macrocell (olmc) each of the macrocells of the gal22lv10 has two primary func- tional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (so and s1), which are nor- mally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc?s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product-term for each olmc, and can therefore be defined by a logic equation. the d flip-flop?s /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either ?on? (dedicated output), ?off? (dedicated input), or ?product-term driven? (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the gal22lv10 has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two olmcs have sixteen product terms (pins 21 and 23). in addition to the product terms available for logic, each olmc has an additional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. the gal22lv10 has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two prod- uct terms are common to all registered olmcs. the asynchronous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations all devices discontinued
specifications gal22lv10 4 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode all devices discontinued
specifications gal22lv10 5 plcc package pinout 2 26 olmc s0 5810 s1 5811 0440 . . . . 0880 3 asynchronous reset (to all registers) 0 4 8 1216202428323640 synchronous preset (to all registers) 12 0000 5764 0044 . . . 0396 27 s0 5808 s1 5809 25 olmc s0 5812 s1 5813 0924 . . . . . 1452 4 5 6 24 olmc s0 5814 s1 5815 1496 . . . . . . 2112 23 olmc s0 5816 s1 5817 2156 . . . . . . . 2860 21 olmc s0 5818 s1 5819 2904 . . . . . . . 3608 20 olmc s0 5820 s1 5821 3652 . . . . . . 4268 olmc s0 5822 s1 5823 4312 . . . . . 4840 10 19 18 olmc s0 5824 s1 5825 4884 . . . . 5324 11 5368 . . . 5720 17 olmc s0 5826 s1 5827 9 7 13 16 8 10 14 16 12 12 16 14 10 8 olmc electronic signature 5828, 5829 ... ... 5890, 5891 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 2 byte 1 byte 0 byte 3 gal22lv10 logic diagram/jedec fuse map all devices discontinued
specifications gal22lv10 6 specifications gal22lv10d 1) the leakage current is due to the internal pull-up resistor on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 3.3v and t a = 25 c commercial i cc operating power v il = 0v v ih = 3.0v unused inputs at v il ? 90 130 ma supply current f toggle = 1mhz outputs open v il input low voltage vss - 0.3 ? 0.8 v v ih input high voltage 2.0 ? 5.25 v i/o high voltage 2.0 ? vcc+0.5 v i il 1 input or i/o low leakage current 0v v in v il (max.) ? ? -100 a i ih input or i/o high leakage current ( v cc-0.2)v v in v cc ??10 a input high leakage current vcc v in 5.25v ? ? 10 a i/o high leakage current vcc v in 4.6v ? ? 20 ma v ol output low voltage i ol = max. vin = v il or v ih ? ? 0.4 v i ol = 500 a vin = v il or v ih ? ? 0.2 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i oh = -100 a v in = v il or v ih v cc-0.2v ? ? v i ol low level output current ? ? 8 ma i oh high level output current ? ? ?8 ma i os 2 output short circuit current v cc = 3.3v v out = 0.5v t a = 25 c -15 ? -80 ma recommended operating conditions commercial devices: ambient temperature (t a ) ............................... 0 to 75 c supply voltage (v cc ) with respect to ground ......................... +3.0 to +3.6v absolute maximum ratings (1) supply voltage v cc .................................... -0.5 to +4.6v input voltage applied ................................. -0.5 to +5.6v i/o voltage applied .................................... -0.5 to +4.6v off-state output voltage applied ................ -0.5 to +4.6v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1.stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). symbol parameter condition min. typ. 3 max. units dc electrical characteristics over recommended operating conditions (unless otherwise specified) all devices discontinued
specifications gal22lv10 7 specifications gal22lv10d -5 min. max. t pd 2 a input or i/o to combinational output 1 4 1 5 ns t co 2 a clock to output delay 1 3 1 3.5 ns t cf 3 ? clock to feedback delay ? 2.5 ? 3 ns t su ? setup time, input or feedback before clock 3 ? 3.5 ? ns t h ? hold time, input or feedback after clock 0? 0 ? ns a maximum clock frequency with 167 ? 143 ? mhz external feedback, 1/(tsu + tco) f max 4 a maximum clock frequency with 182 ? 154 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 250 ? 200 ? mhz no feedback t wh 4 ? clock pulse duration, high 2 ? 2.5 ? ns t wl 4 ? clock pulse duration, low 2 ? 2.5 ? ns t en b input or i/o to output enabled 1 5 1 6 ns t dis c input or i/o to output disabled 1 5 1 6 ns t ar a input or i/o to asynchronous reset of register 1 4.5 1 5.5 ns t arw ? asynchronous reset pulse duration 4.5 ? 5.5 ? ns t arr ? asynchronous reset to clock recovery time 3.5 ? 4 ? ns t spr ? synchronous preset to clock recovery time 3.5 ? 4 ? ns -4 min. max. units parameter test cond 1 . description symbol parameter typical units test conditions c i input capacitance 5 pf v cc = 3.3v, v i = 0v c i/o i/o capacitance 5 pf v cc = 3.3v, v i/o = 0v 1) refer to switching test conditions section. 2) minimum values for t pd and t co are not 100% tested but established by characterization. 3) calculated from fmax with internal feedback. refer to fmax descriptions section. 4) refer to fmax descriptions section. characterized but not 100% tested. com com ac switching characteristics over recommended operating conditions capacitance (t a = 25 c, f = 1.0 mhz) all devices discontinued
specifications gal22lv10 8 specifications gal22lv10c absolute maximum ratings (1) supply voltage v cc .................................... - 0.5 to +5.6v input voltage applied ................................. -0.5 to +5.6v off-state output voltage applied ................ -0.5 to +5.6v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). recommended operating conditions commercial devices: ambient temperature (t a ) ............................. 0 to +75 c supply voltage (v cc ) with respect to ground ......................... +3.0 to +3.6v v il input low voltage vss ? 0.5 ? 0.8 v v ih input high voltage 2.0 ? 5.25 v i il input or i/o low leakage current 0v v in v il (max.) ? ? - 10 a i ih input or i/o high leakage current ( v cc - 0.2)v v in v cc ??10 a v cc v in 5.25 v ??30ma v ol output low voltage i ol = 8ma vin = v il or v ih ? ? 0.4 v i ol = 16 ma vin = v il or v ih ? ? 0.5 v i ol = 0.5 ma vin = v il or v ih ? ? 0.2 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i oh = -0.5 ma v in = v il or v ih vcc-0.45 ? ? v i oh = -100 a v in = v il or v ih vcc-0.2 ? ? v i ol low level output current v ol = 0.4 v ? ? 8 ma v ol = 0.5v ? ? 16 ma i oh high level output current ? ? -4 ma i os 1 output short circuit current v cc = 3.3v v out = 0.5v t a = 25 c -15 ? -60 ma symbol parameter condition min. typ. 2 max. units 1) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2) typical values are at vcc = 3.3v and t a = 25 c commercial i cc operating power v il = 0.0v v ih = 3.0v ? 45 75 ma supply current f toggle = 1mhz outputs open dc electrical characteristics over recommended operating conditions (unless otherwise specified) all devices discontinued
specifications gal22lv10 9 specifications gal22lv10c t pd 2 a input or i/o to combinatorial output 2 7.5 2 10 2 15 ns t co 2 a clock to output delay 1 5 1 6.5 1 10 ns t cf 3 ? clock to feedback delay ? 3 ? 5 ? 5 ns t su ? setup time, input or fdbk before clk 6 ? 7.5 ? 10 ? ns t h ? hold time, input or fdbk after clk 0?0?0?ns a maximum clock frequency with 91 ? 71 ? 50 ? mhz external feedback, 1/(tsu + tco) f max 4 a maximum clock frequency with 111 ? 80 ? 66 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 125 ? 111 ? 83 ? mhz no feedback t wh ? clock pulse duration, high 3.5 ? 4 ? 6 ? ns t wl ? clock pulse duration, low 3.5 ? 4 ? 6 ? ns t en b input or i/o to output enabled 2 10 2 12 2 15 ns t dis c input or i/o to output disabled 2 10 2 12 2 15 ns t ar a input or i/o to asynch. reset of reg. 2 11 2 13 2 20 ns t arw ? asynch. reset pulse duration 6 ? 8 ? 10 ? ns t arr ? asynch. reset to clk recovery time 6 ? 8 ? 10 ? ns t spr ? synch. preset to clk recovery time 6 ? 8 ? 10 ? ns -15 min. max. -10 min. max. units param test cond. 1 description com com -7 min. max. com 1) refer to switching test conditions section. 2) minimum values for tpd and tco are not 100% tested but established by characterization. 3) calculated from fmax with internal feedback. refer to fmax description section. 4) refer to fmax description section. symbol parameter typical units test conditions c i input capacitance 8 pf v cc = 3.3v, v i = 0v c i/o i/o capacitance 8 pf v cc = 3.3v, v i/o = 0v ac switching characteristics over recommended operating conditions capacitance (t a = 25 c, f = 1.0 mhz) all devices discontinued
specifications gal22lv10 10 input or i/o to output enable/disable registered output combinatorial output input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max clk (w/o fdbk) t wh t wl 1/ f max clock width registered output clk t arw t ar t arr input or i/o feedback driving ar f max with feedback clk registered feedback t cf t su 1/ f max (internal fdbk) asynchronous reset synchronous preset t en t dis input or i/o feedback output valid input input or i/o feedback t pd combinatorial output registered output clk input or i/o feedback driving sp t su t h t co t spr switching waveforms all devices discontinued
specifications gal22lv10 11 f max with internal feedback 1/( t su+ t cf) note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/ fmax - tsu). the value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combinatorial output is equal to tcf + tpd. f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. register logic array t co t su clk f max with external feedback 1/( t su+ t co) note: fmax with external feedback is calculated from measured tsu and tco. register logic array clk t su + t h clk register logic array t cf t pd f max descriptions all devices discontinued
specifications gal22lv10 12 *c l includes test fixture and probe capacitance. test point z 0 = 50, c l = 35pf* from output (o/q) under test +1.45v r 1 input pulse levels gnd to 3.0v input rise and fall times 1.5ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure output load conditions (see figure) test condition r 1 c l a5 0 35pf b high z to active high at 1.9v 50 35pf high z to active low at 1.0v 50 35pf c active high to high z at 1.9v 50 35pf active low to high z at 1.0v 50 35pf input pulse levels gnd to 3.0v input rise and fall times 2.0ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure) test condition r 1 r 2 c l a 316 348 35pf b active high 316 348 35pf active low 316 348 35pf c active high 316 348 5pf active low 316 348 5pf test point c * l from output (o/q) under test +3.3v *c l includes test fixture and probe capacitance r 2 r 1 gal22lv10d: switching test conditions gal22lv10c: switching test conditions all devices discontinued
specifications gal22lv10 13 electronic signature an electronic signature (es) is provided in every gal22lv10 device. it contains 64 bits of reprogrammable memory that can contain user-defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is al- ways available to the user independent of the state of the security cell. the electronic signature is an additional feature not present in other manufacturers' 22v10 devices. to use the extra feature of the user- programmable electronic signature it is necessary to choose a lattice semiconductor 22v10 device type when compiling a set of logic equations. in addition, many device programmers have two separate selections for the device, typically a gal22lv10 and a gal22v10-ues (ues = user electronic signature) or gal22v10- es. this allows users to maintain compatibility with existing 22v10 designs, while still having the option to use the gal device's ex- tra feature. the jedec map for the gal22lv10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. however, the gal22lv10 device can still be programmed with a standard 22v10 jedec map (5828 fuses) with any qualified device programmer. security cell a security cell is provided in every gal22lv10 device to prevent unauthorized copying of the array patterns. once programmed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the de- vice, so the original configuration can never be examined once this cell is programmed. the electronic signature is always available to the user, regardless of the state of this control cell. latch-up protection gal22lv10 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. device programming gal devices are programmed using a lattice semiconductor- approved logic programmer, available from a number of manu- facturers (see the the gal development tools section). complete programming of the device takes only a few seconds. erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. typical input pull-up characteristic input voltage (v) input current ( a) -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state conditions. the gal22lv10 device includes circuitry that allows each regis- tered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if nec- essary, approved gal programmers capable of executing test vectors perform output register preload automatically. input buffers gal22lv10 devices are designed with ttl level compatible input buffers. these buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar ttl devices. the input and i/o pins on the gal22lv10d also have built-in active pull-ups. as a result, floating inputs will float to a ttl high (logic 1). however, lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to an adjacent active input, vcc, or ground. doing so will tend to improve noise immu- nity and reduce icc for the device. (see equivalent input and i/o schematics on the following page.) all devices discontinued
specifications gal22lv10 14 typ. vref = vcc typical output typ. vref = vcc typical input circuitry within the gal22v10 provides a reset signal to all reg- isters during power-up. all internal registers will have their q out- puts set low after a specified time (tpr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. the timing diagram for power-up is shown below. because of the asyn- chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the gal22v10. first, the vcc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in normal sys- tem operation, avoid clocking the device until all input and feed- back path setup times have been met. the clock must also meet the minimum pulse width requirements. vcc pin vref tri-state control active pull-up circuit (gal22lv10d only) feedback (to input buffer) pin feedback data output vcc pin vcc vref active pull-up circuit (gal22lv10d only) esd protection circuit esd protection circuit vcc pin vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register power-up reset input/output equivalent schematics all devices discontinued
specifications gal22lv10 15 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.95 0.975 1 1.025 1.05 3.00 3.15 3.30 3.45 3.60 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -8 -4 0 4 8 12 16 20 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -4 0 4 8 12 16 20 0 50 100 150 200 250 300 rise fall gal22lv10d: typical ac and dc characteristic diagrams all devices discontinued
specifications gal22lv10 16 vol vs iol iol (ma) vol (v) 0 0.2 0.4 0.6 0.8 1 0.00 5.00 10.00 15.00 20.00 25.00 30.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 0.00 5.00 10.00 15.00 20.00 voh vs ioh ioh(ma) voh (v) 2.7 2.8 2.9 3 3.1 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.60 0.80 1.00 1.20 1.40 3.00 3.15 3.30 3.45 3.60 normalized icc vs temp temperature (deg. c) normalized icc 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 1 2 3 4 5 6 7 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 input clamp (vik) vik (v) iik (ma) 0 5 10 15 20 25 30 35 -2.00 -1.50 -1.00 -0.50 0.00 gal22lv10d: typical ac and dc characteristic diagrams all devices discontinued
specifications gal22lv10 17 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.95 0.975 1 1.025 1.05 3.00 3.15 3.30 3.45 3.60 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -8 -4 0 4 8 12 16 20 24 28 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -6 -2 2 6 10 14 18 22 26 0 50 100 150 200 250 300 rise fall gal22lv10c: typical ac and dc characteristic diagrams all devices discontinued
specifications gal22lv10 18 vol vs iol iol (ma) vol (v) 0 0.2 0.4 0.6 0.8 1 0.00 10.00 20.00 30.00 40.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 0.00 5.00 10.00 15.00 20.00 voh vs ioh ioh(ma) voh (v) 2.7 2.8 2.9 3 3.1 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.60 0.80 1.00 1.20 1.40 3.00 3.15 3.30 3.45 3.60 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.80 1.00 1.20 1.40 1.60 1.80 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 1 2 3 4 5 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 input clamp (vik) vik (v) iik (ma) 0 10 20 30 40 50 60 -2.00 -1.50 -1.00 -0.50 0.00 gal22lv10c: typical ac and dc characteristic diagrams all devices discontinued
specifications gal22lv10 19 revision history date version change summary - 22lv10_05 previous lattice release. august 2006 22lv10_06 updated for lead-free package options. august 2008 22lv10_07 correction for dc electrical characteristics. all devices discontinued

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